A wide variety of integrated circuit memories are available for storing data. One type of memory is the dynamic random access memory (DRAM). A DRAM is designed to store data in memory cells formed as capacitors. The data is stored in a binary format; a logical "one" is stored as a charge on a capacitor, and a logical "zero" is stored as a discharged capacitor. The typical DRAM is arranged in a plurality of addressable rows and columns. To access a memory cell, a row is first addressed so that all memory cells coupled with that row are available for accessing. After a row has been addressed, at least one column can be addressed to pinpoint at least one specific memory cell for either data input or output. The data stored in the memory cells is, therefore, accessible via the columns.
With the constant development of faster computer and communication applications, the data rates in which a memory circuit must operate continue to increase. To address the need for increased data rates, a variety of DRAMs are commercially available. These memories are produced in a variety of designs which provide different methods of reading from and writing to the dynamic memory cells of the memory. One such method is page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell array and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. Page mode DRAMs require access steps which limit the communication speed of the memory circuit.
An alternate type of memory circuit is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory circuit can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on the communication lines. Column access times are, therefore, "masked" by providing the extended data output. A more detailed description of a DRAM having EDO features is provided in the "1995 DRAM Data Book" pages 1-1 to 1-30 available from Micron Technology, Inc. Boise, Id., which is incorporated herein by reference.
Memory circuits which have more than eight I/O communication lines typically require multiple column address strobe signals (CAS*). These signals are used to read from the memory and write to the memory in separate bytes. That is, one access signal controls one byte of the I/O and the other access signal controls another byte of the I/O. Using two or more column address strobe signals to control the input and output of the memory, however, increases current consumption and reduces the speed of the memory due to skew between the address signals.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory circuit which can be operated using multiple address signals while operating at fast data output rates.